The present invention relates to microscopic field emitter tips manufactured by microchip fabrication techniques in dense field emitter tip arrays and, in particular, to a method for creating a field emitter tip within a substrate layered with alternating non-conductive and conductive layers using a single photolithography step followed by a number of different etching steps.
The present invention relates to design and manufacture of silicon-based field emitter tips. A brief discussion of field emission and the principles of design and operation of field emitter tips is therefore first provided in the following paragraphs, with reference to FIG. 1.
When a wire, filament, or rod of a metallic or semiconductor material is heated, electrons of the material may gain sufficient thermal energy to escape from the material into a vacuum surrounding the material. The electrons acquire sufficient thermal energy to overcome a potential energy barrier that physically constrains the electrons to quantum states localized within the material. The potential energy barrier that constrains electrons to a material can be significantly reduced by applying an electric field to the material. When the applied electric field is relatively strong, electrons may escape from the material by quantum mechanical tunneling through a lowered potential energy barrier. The greater the magnitude of the electrical field applied to the wire, filament, or rod, the greater the current density of emitted electrons perpendicular to the wire, filament, or rod. The magnitude of the electrical field is inversely related to the radius of curvature of the wire, filament, or rod.
FIG. 1 illustrates principles of design and operation of a silicon-based field emitter tip. The field emitter tip 102 rises to a very sharp point 104 from a silicon-substrate cathode 106, or electron source. A localized electric field is applied in the vicinity of the tip by a first anode 108, or electron sink, having a disk-shaped aperture 110 above and around the point 104 of the field emitter tip 102. A second cathode layer 112 is located above the first anode 108, also with a disk-shaped aperture 114 aligned directly above the disk-shaped aperture 110 of the first anode layer 108. This second cathode layer 112 acts as a lens, applying a repulsive electronic field to focus the emitted electrons into a narrow beam. The emitted electrons are accelerated towards a target anode 118, impacting in a small region 120 of the target anode defined by the direction and width of the emitted electron beam 116. Although FIG. 1 illustrates a single field emitter tip, silicon-based field emitter tips are commonly micro-manufactured by microchip fabrication techniques as regular arrays, or grids, of field emitter tips.
Currently available methods for fabricating arrays of field emitter tips require either various selective silicon oxidation techniques or complex metal deposition and lift-off processes. Currently available methods require precise alignment and sequential masking deposition steps. Designers and manufacturers of microfield emitter tips arrays have recognized the need for a more simple microfabrication methodology for constructing silicon-based field emitter tips, particularly for fabricating silicon-based emitter tips on a semiconductor surface above microelectronic devices such as a field-effect transistors or diodes.
One embodiment of the present invention is a method for fabricating a silicon-based field emitter tip on a substrate that may already contain microelectronic devices. The silicon substrate is first layered with alternating dielectric and metallic layers by standard microchip fabrication techniques. A photoresist layer is then added, and is photolithographically patterned to produce a rectangular or annular groove in the photoresist. The layered substrate is then exposed to an anisotropic etch medium to create a tube-like slot through the dielectric and metallic layers, producing a layered, rectangular or cylindrical column or pinnacle on the surface of the substrate. The layered substrate is then exposed to an isotropic etch medium that creates a conical field emitter tip within the silicon substrate below the tube-like slot etched through the dielectric and metallic layers, and removing the rectangular or cylindrical column to leave a rectangular or cylindrical well through the dielectric and metallic layers. Finally, a third etching medium is used to slightly pull back the dielectric layers from the walls of the aperture. In an optional step, a thin metallic coating can be deposited by a sputter deposition technique onto the surface of the conical silicon field emitter tip.
A second embodiment of the present invention is similar to the first, but uses an anisotropic silicon etch to form the emitter tip. In this embodiment, the silicon substrate is first layered with alternating dielectric and metallic layers by standard microchip fabrication techniques. A photoresist layer is then added, and is photolithographically patterned to produce a rectangular or annular groove in the photoresist. The layered substrate is then exposed to an anisotropic etch medium to create a tube-like slot through the dielectric and metallic layers, producing a layered, rectangular or cylindrical column or pinnacle on the surface of the substrate. The layered substrate is then exposed to an anisotropic etch medium, such as potassium hydroxide, that creates a pyramid shaped filed emitter tip within the silicon substrate below the tube-like slot etched through the dielectric and metallic layers, and removing the rectangular or cylindrical column to leave a rectangular or cylindrical well through the dielectric and metallic layers. Finally, a third etching medium is used to slightly pull back the dielectric layers from the walls of the aperture. In an optional step, a thin metallic coating can be deposited by a sputter deposition technique onto the surface of the silicon field emitter tip.